In a system of the kind in which an image input/output unit and an image control unit, for example, are controlled by independent CPUs, the conventional practice when sending and receiving variable-length messages between the units is for the CPUs to control communication controllers on per-byte (eight-bit) basis.
In this example of the prior art, a CPU interrupt is generated byte by byte. When data communication takes place at high speed, therefore, some data may failed to be acquired and other processing by the CPU may be adversely affected. Depending upon the communication controller, it is possible to use a FIFO buffer to reduce the frequency with which CPU interrupt occurs, though often the communication controller that is incorporated within a low-cost single-chip microcontroller does not come equipped with this function. A microcontroller that is available can perform data transfer without the intervention of a CPU by using a combination of a DMA controller and a communication controller. However, since the length of received messages is indeterminate, the DMA transfer length cannot be set in advance. This necessitates an operation in which a CPU polls the counter of the DMA controller. Such a microcontroller, therefore, is not suitable for receiving variable-length messages as is.
Meanwhile, there is a tendency for the amount of data transferred between devices to increase as functions become more sophisticated. For example, when the image processing speed of an image input/output unit rises, communication time allowed for control between pages tends to shorten. Hence there is a demand for ever higher data communication speed.